Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. The individual wafers are subjected to a number of processing operations to reduce the thickness of the wafer, remove damage caused by the slicing and/or other processing operations, and to create at least one highly reflective surface (e.g., on a front surface of the wafer).
In addition to having at least one highly reflective surface, semiconductor wafers for advanced applications need to have edges that are smooth, damage-free, and polished. Damaged edges may cause edge slip during thermal processing of the wafer. In addition, rough or pitted edges may trap particles that can be later released in a wet cleaning bath. The released particles may then undesirably migrate to the surface of the wafer. Furthermore, various films are deposited onto the wafer surface in some applications, which may deposit at the edge of the wafer. If the edge is not sufficiently smooth, residual film deposits at the edge may flake off. The flakes may come into contact with the surface of the wafer thereby causing surface defects.
To avoid these and other potential problems, the edges of the wafer are polished. In addition to the edge, semiconductor wafers for advanced applications have an orientation notch that must also be polished. Typical notch and edge polishing tools remove dry wafers from a process cassette, aligns the notch in the wafers, polishes the notch in the wafers, polishes the edge of the wafers, scrubs and/or cleans the wafers, spin dries the wafers, and then returns the dry wafers to the process cassette where the wafers can be moved to the next station.
Semiconductor wafers for advanced applications are often double-sided polished (commonly referred to as DPOL) to obtain highly reflective surfaces on the wafer. The reason for using double-sided polishing instead of other surface polishing methods is two fold. The double-sided polishing process generally produces a wafer that is extremely flat, parallel and with minimal surface topology (nanotopology) on both the front and back surfaces of the wafer. Good flatness is required for advanced lithography of scanners to permit even smaller sizes for the so-called critical dimension (CD). Low surface topology, especially on the back surface of the wafer is required to maximize CMP film removal uniformity and minimize film over-polish or film under-polish.
Accordingly, semiconductor wafers for advanced applications are commonly both edge polished and double-sided polished. Often, the edge of the wafer is polished first because the edge-polishing process can contaminate the front and back surface of the wafer with silica, which is one of the constituents of polishing slurry used during edge polishing. After the edge is polished, the wafer is double-side polished. Unfortunately, during the double-sided polishing process, the polished edge of the wafer is damaged in at least two ways. Because of the high pH of the polishing slurry, the temperature of the wafer and slurry, and duration of the process, the edge of the wafer is roughened by the alkaline etching of the slurry. Since the edge of the wafer is not in contact with a polishing pad that contains slurry, the polished edge is roughened because of etching in the absence of polishing. In addition, an apex of the edge of the wafer contacts a plastic-lined insert of a double-sided polishing carrier. During rotation of the wafer during the double-sided polishing process, the edge of the wafer wears against the insert and both the wafer edge (apex) and the insert are degraded. As a result, the apex of the edge of the wafer develops striations.
If, however, the edge of the wafer is polished after double-sided polishing, a smooth edge can be produced. Any roughening by alkaline etching or any abrasion striations produced by the carrier insert can be removed by edge polishing. Unfortunately, the polished surfaces of the wafer can be stained or damaged by a wafer vacuum chuck that is used to hold the wafer during edge polishing. FIG. 1, for example, shows a chuck mark that was formed by the vacuum chuck during edge polishing of the wafer. FIG. 2 shows a stackmap from a Raytex Corporation's (Tokyo, Japan) EdgeScan B+ surface inspection tool of the chucked side of 20 wafers. As shown, the wafer vacuum chuck can damage the chucked surface of the wafer (i.e., can cause marks and/or stains).
The chuck marks and stains are difficult to remove from the wafer. If the wafer is chucked on the side to be finish polished, the chuck mark acts as a mask and may alter the flatness and/or topology of the wafer. If the wafer is chucked on the back surface, the chuck mark alters the topology of the back surface and may possibly impact CMP film uniformity.